vsync width register is generaly set as 8. and read as 2 line-char.
Setting 2 on games run them fine but not with demo. In fact in CRTC0 we read VSYNC step per step (Vcc), not per line-char.
With CRTC0 you can set a VSYNC based on register.
I’m trying to implement CRTC0 in FPGAmstrad.
But I don’t know witch demo is CRTC1 or CRTC0
I need to know witch demo is pure CRTC0.
For sample, Logon’s run don’t display 3D gameboy on my CRTC0, is this demo part just for CRTC1 ?
Wake Up does pass the “CRTC0 detection” but don’t run at normal speed.
This question is a bit confusing to read.
What does “read as 2 line-char” mean? If R3=#8x, then the CRTC will create a VSYNC of 8 scanlines. The Gate Array will use this to create a composite sync signal of 4 scanlines.
What does “Setting 2” mean? Is it about to set R3=#2x? In this case the CRTC will only create 2 scanlines with VSYNC. I’m not sure, if this is sufficient for the Gate Array to create the composite signal. And even if, I’m not sure if the composite signal is long enough so that the monitor can synchronize to it.
What is a CRTC0 demo, what a CRTC1 demo? A demo can run on both CRTCs or only on one of them, based on a special usage of some registers. This need not be register R3, it can as well be another one.
For detailed information I suggest the “Amstrad CPC CRTC Compendium” (AC3) from @Longshot of Logon System. Set at https://shaker.logonsystem.eu/ .
I cannot tell much about other demos, but I myself wrote a small pre-demo (currently no music and no scroll text) that executes some tests to detect the CRTC type and then makes use of register R0 for scanline selection. See at https://codeberg.org/lightforce6128/cpc-circles#circles .
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More specifically, in ACCC you can consult chapter 14.1 for setting the HSYNC lengths (and VSYNC on CRTC 0, 3, 4) and chapter 17.1 more specifically on VSYNC.
To avoid compatibility issues, it’s recommended to set R3=#0x so that the VSYNC on 0, 3, 4 has 16 lines, as on CRTC 1 and 2. The GATE ARRAY generates a composite signal of a maximum of 4 lines between the 3rd and 6th lines (by line, I mean the HSYNC signal) after the CRTC’s VSYNC signal. However, it’s useful to program more than 6 lines (and therefore 16 for uniformity) to maintain the state of the VSYNC signal that the Z80A can read from the PPI.
You’re not clear about the context you used to run the demos you mentioned. If you’re talking about actual CPCs (and not an FPGA, where you mentioned shortening VSYNC to 2 lines), then it’s rather strange because the “Logon’s run” works on all CRTCs. If you were talking about the FPGA or some workaround that reduced VSYNC to 2 (as is possible on CRTC 0), then it was simply pointless to do so.
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I had a trap for R3Vwidth/=x"8"
if R3Vwidth/=x"8" and etat_vsync=DO_VSYNC then
etat_vsync:=DO_NOTHING;
crtc0_state:=STATE_R3VWIDTH_3; – it’s a trap
end if;
Logon’s run trapped : it does R3Width=0
Bruce lee not trapped.
Arkanoid not trapped
Buggy boy bug is not trapped so it’s not around R3Vwidth
Is R3Width at 0 does? a line or nothing? If it’s a line is it so 1 does not another line?
You should really consult chapter 14.1 of ACCC, as I mentioned earlier.
If you set the most significant nibble of R3 to 1, then CRTCs 0, 3, and 4 generate one line of VSYNC.
If you set this nibble to 0, then these CRTCs generate 16 lines (not 0) to remain compatible with models that don’t have this feature (like CRTCs 1 and 2, which always generate 16 lines because the bits in this nibble are inoperative).